1. Field of the Invention
Embodiments of the present invention generally relate to a hardware emulator for emulating a system composed of logic gates, and more particularly, to a hardware emulator having a variable input primitive.
2. Description of the Related Art
Hardware emulators are programmable devices used in the verification of hardware design. A common method of hardware design verification is to use processor-based hardware emulator to emulate the design. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
An exemplary hardware emulator is described in commonly assigned U.S. Pat. No. 6,618,698 titled “Clustered Processors in an Emulation Engine”, which is hereby incorporated by reference in its entirety. Hardware emulators allow engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate the hardware.
The complexity and number of logic gates present within an integrated circuit has increased significantly in the past several years. Hardware emulators need to improve in efficiency to keep pace with the increased complexity of integrated circuits. The speed and logic gate efficiency with which a hardware emulator emulates an integrated circuit is one of the most important benchmarks of the emulator's efficiency, and also one of the emulator's most important selling factors in the emulator market.
A hardware emulator comprises multiple processors, which are generally a portion of a processor module, where the processor module comprises a processor as well as related supporting circuitry. The processor modules are arranged into groups of processor modules called dusters, and the clusters of processor modules collectively comprise the emulation engine that forms a core element of a hardware emulator. During each process cycle, each processor is capable of emulating a logic gate, mimicking the function of a logic gate in an integrated circuit. The processors are arranged to compute results in parallel, in the same way logic gates present in an integrated circuit compute many results in parallel. This creates a chain of logic similar to what occurs in an integrated circuit. In the chain of logic, efficient communication between processors is crucial.
A processor receives a small amount of input data, typically four bits, and utilizes a “primitive” to emulate a logical function that would otherwise be performed by a logic gate of the hardware being emulated. In a process known as evaluation, a primitive translates the input data into an output bit to emulate the function performed by the gate being emulated. The resulting bit is the output that would be generated by the one or more gates being emulated. In this manner, a primitive is used to evaluate the function performed by the gate. To facilitate such an evaluation, the primitive comprises a lookup table that contains a logic table of all the possible results (output bit values) of the function being evaluated. The logic table maps all possible input data combinations to all possible bit values. A four input primitive comprises a logic table with sixteen bits of output data to be able to produce all possible valid results of the function. The four input bits are used, in essence, as an address to select a location in the lookup table containing a data bit that forms the output of the function for a particular set of four input bits. By setting an appropriate mapping of input bits to output bit (i.e., by loading appropriate table values), the logic table provides the valid result of any function that uses four input bits or less.
In certain emulators where the gates to be emulated have a large number of input bits (e.g., greater than four bits), it is desirable to have a processor utilize primitives having more than four bits of input data. One solution decomposes the function of large input gates into many levels of four input primitives. Each level performs a portion of the total gate function and the output of each level is combined with the output of other primitives representing other levels to achieve a final output of the large input gate. To facilitate such a multi-level evaluation of a gate, the input data is divided into many portions and a separate primitive processes each portion. Each evaluation of a data portion occurs during a single step of the emulation cycle. As more primitives are required to evaluate each data portion, more steps are required to calculate the final output for a given gate. Further, as the number of primitives increases, the chip area required for the primitives increases. For example, an N-bit×N-bit multiplier requires 2×N-bit product. When N=2, only four input primitives are requires. However, when N=4, a total of 248 four input primitives need to be evaluated. When N=8, sixteen 16 input primitives would be evaluated to provide the product. Each sixteen input primitive requires 8095 four input primitives. The full product requires 129,520 four input primitives. Thus, such a solution is inefficient in its use of emulation steps as well as its use of chip area.
In a second solution used in the prior art, a larger primitive may be used to emulate a large input gate. A larger primitive is able to perform faster calculations since there are fewer levels of logic to evaluate, i.e., a single primitive can represent many levels of logic. However, because the size of the lookup table (i.e., the hardware that stores the logic table) used by the primitive is exponentially related to the input size of the primitive, larger primitives require substantially larger chip areas to accommodate the lookup tables. Consequently, the practically achievable size of the hardware emulator chip ultimately limits the use of large primitives.
Thus, there is a need in the art for a method and apparatus that improves primitive utilization in a hardware emulator to facilitate large input gate emulation.